Final faulty core recovery mechanisms for a two-dimensional network on a processor array
US8990616B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Feb 22, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/557
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention relate to faulty recovery mechanisms for a two-dimensional (2-D) network on a processor array. One embodiment comprises a processor array including multiple processors core circuits, and a redundant routing system for routing packets between the core circuits. The redundant routing system comprises multiple switches, wherein each switch corresponds to one or more core circuits of the processor array. The redundant routing system further comprises multiple data paths interconnecting the switches, and a controller for selecting one or more data paths. Each selected data path is used to bypass at least one component failure of the processor array to facilitate full operation of the processor array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.