Gateway model routing with slits on wires
US8990756B2 · kind B2 · utility
1Cited by
5References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2013 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for routing at least one conductor includes generating the at least one conductor within a bounded region on a planar surface in accordance with a template, and placing at least one slit in the conductor when the conductor overlaps a specified region of the bounded region in accordance with a specified pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.