Method for forming pad in wafer with three-dimensional stacking structure
US8993411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Feb 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01078
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a pad in a wafer with a three-dimensional stacking structure is disclosed. The method includes bonding a device wafer that includes an Si substrate and a handling wafer, thinning a back side of the Si substrate, depositing an anti-reflective layer on the thinned back side of the Si substrate, depositing a back side dielectric layer on the anti-reflective layer, defining a space for a pad in the back side dielectric layer and forming vias that pass through the back side dielectric layer and the anti-reflective layer and contact back sides of super contacts which are formed on the Si substrate, filling one or more metals in the vias and the defined space for the pad, and removing a remnant amount of the metal filled in the space for the pad through planarization by a CMP (chemical mechanical polishing) process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.