Stacked carbon-based FETs
US8994080B2 · kind B2 · utility
3Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Aug 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/08
Abstract
Stacked transistor devices include a lower channel layer formed on a substrate; a pair of vertically aligned source regions formed over the lower channel layer, where the pair of source regions are separated by an insulator; a pair of vertically aligned drain regions formed on the lower channel layer, where the pair of drain regions are separated by an insulator; a pair of vertically aligned gate regions formed on the lower gate dielectric layer; and an upper channel layer formed over the source regions, drain regions, and gate regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.