Semiconductor device with gate stacks having stress and method of manufacturing the same

US8994119B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Huaxiang Yin · Beijing, CN
• Zuozhen Fu · Beijing, CN
• Qiuxia Xu · Beijing, CN
• Chao Zhao · Thuwal, SA
• Dapeng Chen · Beijing, CN

Key dates

• Filing date: Apr 11, 2012
• Grant date: Mar 31, 2015
• Expiry date: Sep 8, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/693

Abstract

The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobilit…