Device bond pads over process control monitor structures in a semiconductor die

US8994148B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Achim Gratz · Dresden, DE
• Scott Wallace · Stillwater, US
• Tobias Jacobs · Mannheim, DE

Key dates

• Filing date: Feb 19, 2013
• Grant date: Mar 31, 2015
• Expiry date: Feb 19, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/1306
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor die includes a semiconductor substrate having an edge region surrounding an active region, the active region containing devices of an integrated circuit. The semiconductor die further includes interconnect wiring over the active region in an interlayer dielectric and electrically connected to the devices in the active region, and ancillary wiring over the edge region in the interlayer dielectric and isolated from the interconnect wiring and the devices in the active device region. The interlayer dielectric is passivated, and bond pads are provided over the interconnect wiring and electrically connected to the interconnect wiring through openings in the passivation over the active region. Additional bond pads are provided over the ancillary wiring and are electrically connected to the interconnect wiring through additional openings in the passivation over the active region.