Connection of a chip provided with through vias
US8994172B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Apr 29, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Apr 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip provided with through vias wherein the vias are formed of an opening with insulated walls coated with a conductive material and filled with an easily deformable insulating material, elements of connection to another chip being arranged in front of the easily deformable insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.