Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit
US8994402B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jun 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018507
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A level shifter and integrated level shifter and metastability resolution flop circuit are disclosed. A circuit includes a generation circuit, in a first voltage domain, coupled to receive a logic signal via a single-ended input and configured to generate true and complementary values of the logic signal. The circuit further includes a storage circuit coupled to receive the true and complementary values of the logic signal from the generation circuit. The storage circuit is configured to store the true and complementary values of the logic signal. The storage circuit is in a second voltage domain. The circuit further includes an output circuit coupled to the storage circuit and configured to provide a differential output signal having true and complementary values corresponding to the true and complementary values of the logic signal. The circuit may be combined with a latch circuit coupled to receive the differential output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.