High-performance scalable read-only-memory cell
US8995164B2 · kind B2 · utility
2Cited by
1References
19Claims
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Key dates
| Filing date | Jun 27, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Dec 21, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/25
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.