Method of operating FET low current 3D Re-RAM
US8995169B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Sep 12, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operating ReRAM memory is disclosed herein. The memory cells may be trained prior to initially programming them. The training may help to establish a percolation path. In some aspects, a transistor limits current of the memory cell when training and programming. A higher current limit is used during training, which conditions the memory cell for better programming. The non-memory may be operated in unipolar mode. The memory cells can store multiple bits per memory cell. A memory cell can be SET directly from its present state to one at least two data states away. A memory cell can be RESET directly to the state having the next highest resistance. Program conditions, such as pulse width and/or magnitude, may depend on the state to which the memory cell is being SET. A higher energy can be used for programming higher current states.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.