Reducing the programming current for memory matrices
US8995190B2 · kind B2 · utility
0Cited by
12References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 24, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jan 25, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.