Patent · US Active

Method of programming selection transistors for NAND flash memory

US8995192B2 · kind B2 · utility

4Cited by
0References
2Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMar 28, 2012
Grant dateMar 31, 2015
Priority date
Expiry dateJun 14, 2033

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C16/34
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.