Patent · US Active

Write and read collision avoidance in single port memory devices

US8995210B1 · kind B1 · utility

4Cited by

5References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Norbert Hagspiel · Wissen, DE
Sascha Junghans · Herrenberg, DE
Matthias Klein · Poughkeepsie, US
Joerg Walter · Lörrach, DE

Key dates

Filing date	Nov 26, 2013
Grant date	Mar 31, 2015
Priority date	—
Expiry date	Nov 26, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2209
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method of avoiding a write collision in single port memory devices from two or more independent write operations is described. A first write operation having a first even data object and a first odd data object is received from a first data sender. A second write operation having a second even data object and a second odd data object is received from a second data sender at substantially the same time as the first write operation. The second write operation is delayed so that the first even data object writes to a first single port memory device at a different time than the second even data object writes to the first single port memory device. The second write operation is delayed so that the first odd data object writes to a second single port memory device at a different time than the second odd data object.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.