Clock domain crossing serial interface, direct latching, and response codes
US8996736B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2013 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Jul 25, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.