Multi-chip memory devices and methods of controlling the same
US8996759B2 · kind B2 · utility
4Cited by
3References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2011 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | May 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-chip memory device and a method of controlling the same are provided. The multi-chip memory device includes a first memory chip; and a second memory chip sharing an input/output signal line with the first memory chip, wherein each of the first memory chip and the second memory chip determines whether to execute a command unaccompanied by an address, by referring to a history of commands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.