Cache memory controller
US8996815B2 · kind B2 · utility
1Cited by
1References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | Apr 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) may include a cache memory, and a cache memory controller coupled to the cache memory. The cache memory controller may be configured to receive a cache miss associated with a memory location, issue pre-fetch requests, each pre-fetch request having a quality of service (QoS), and determine if a pre-fetch request has issued for the memory location associated with the cache miss.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.