Manufacturing process of memory cells
US8999796B2 · kind B2 · utility
0Cited by
0References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 7, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Nov 7, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/768
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating at least one cell of a semiconducting component includes positioning a first conducting polysilicon-type layer on a substrate, above an insulating oxide-type layer. The production of at least one trench within the first conducting layer is included to form two electrically unlinked distinct conducting parts intended to form two transistor gates of respectively two distinct twin cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.