Vertical IGBT adjacent a RESURF region
US9000478B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Feb 27, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A semiconductor apparatus includes a substrate having a device region and a peripheral region located around the device region. A first semiconductor region is formed within the device region, is of a first conductivity type, and is exposed at an upper surface of the substrate. Second-fourth semiconductor regions are formed within the peripheral region. The second semiconductor region is of the first conductivity type, has a lower concentration of the first conductivity type of impurities, is exposed at the upper surface, and is consecutive with the first semiconductor region directly or indirectly. The third semiconductor region is of a second conductivity type, is in contact with the second semiconductor region from an underside, and is an epitaxial layer. The fourth semiconductor region is of the second conductivity type, has a lower concentration of the second conductivity type of impurities, and is in contact with the third semiconductor region from an underside.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.