Wafer-level thin chip integration
US9000587B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jun 28, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level package device and techniques for fabricating the device are described that include embedding a silicon chip onto an active device wafer or a passive device wafer, where the embedded silicon chip is a thin chip (e.g., <50 μm). In implementations, the wafer-level package device that employs the techniques of the present disclosure includes an active device wafer, a thin integrated circuit chip, an encapsulation structure covering at least a portion of the active device wafer and the thin integrated circuit chip, a redistribution layer structure, and at least one solder bump for providing electrical interconnectivity. Once the wafer is singulated into semiconductor devices, each semiconductor device including the embedded thin integrated circuit chip may be mounted to a printed circuit board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.