Programmable delay circuit
US9000822B2 · kind B2 · utility
9Cited by
34References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Apr 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/0015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay circuit includes at least one main inverter configured to receive an input signal and output a delayed output signal and at least one switchable inverter connected in parallel with the main inverter circuit. The switchable inverter is configured to decrease a delay between the input signal and the delayed output signal based on the switchable inverter being turned on.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.