Mid-band PSRR circuit for voltage controlled oscillators in phase lock loop
US9000857B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0995
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.