Pseudo retention till access mode enabled memory
US9001570B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Nov 16, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory configurable to be used in an RTA mode includes an input latch configured to receive an input address bus and to generate a latched address bus that corresponds to a memory location. An address flop is configured to save the latched address and to generate a flopped address. A first block address pre-decoder stage is configured to generate a pre-decoded latched address to an RTA generation logic in response to the latched address bus; and a second block address pre-decoder configured to generate a pre-decoded flopped address to the RTA generation logic in response to the flopped address. The RTA generation logic generates an RTA enable signal one clock cycle before a memory block access, to activate a memory block corresponding to the memory location, such that an array supply voltage of the memory block starts charging one clock cycle before a memory block access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.