Three-dimensional two port register file
US9001611B1 · kind B1 · utility
7Cited by
1References
20Claims
0Family size
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Key dates
| Filing date | Nov 1, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Nov 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit that includes an array of memory cells. The integrated circuit also includes a write address row decoder having a plurality of write row outputs and a write address column decoder having a plurality of write column outputs. A write logic array is electrically connected to the write row outputs and the write column outputs and has a separate write word line (WWL) output electrically connected to each cell in the array of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.