Method and apparatus of high speed encryption and decryption
US9002002B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2013 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A hardware architecture for encryption and decryption device can improve the encryption and decryption data rate by using parallel processing, and pipeline operation, and save footprint by sharing hardware components. The hardware architecture can also be associated with a memory to protect the information stored at the memory. The encryption device can include a tweaking value manager to generate an array of tweaking values corresponding to the array of data blocks based on a tweaking encryption key, a first encryption unit to encrypt a first portion of the array of data blocks into a first portion of encrypted data blocks based on corresponding tweaking values and a data encryption key, a second encryption unit to encrypt a second portion of the array of data blocks, and a data block combiner to combine the first portion of encrypted data blocks and the second portion of encrypted data blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.