Wire like link for cycle reproducible and cycle accurate hardware accelerator
US9002693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 2, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jan 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
First and second field programmable gate arrays are provided which implement first and second blocks of a circuit design to be simulated. The field programmable gate arrays are operated at a first clock frequency and a wire like link is provided to send a plurality of signals between them. The wire like link includes a serializer, on the first field programmable gate array, to serialize the plurality of signals; a deserializer on the second field programmable gate array, to deserialize the plurality of signals; and a connection between the serializer and the deserializer. The serializer and the deserializer are operated at a second clock frequency, greater than the first clock frequency, and the second clock frequency is selected such that latency of transmission and reception of the plurality of signals is less than the period corresponding to the first clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.