Confirming store-to-load forwards
US9003225B2 · kind B2 · utility
2Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2012 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jun 8, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.