System and method for reducing power consumption of integrated circuit
US9003351B1 · kind B1 · utility
1Cited by
7References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2014 |
| Grant date | Apr 7, 2015 |
| Priority date | — |
| Expiry date | Jan 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing power consumption of an integrated circuit with an EDA tool by analyzing and modifying a layout design having a plurality of nets across multiple metal layers. The method includes identifying long nets in the layout design, determining an interconnect capacitance of each of the long nets, determining a net level switching activity of each of the long nets, generating a high power impact list using the interconnect capacitance and the switching activity of each of the long nets, modifying a metal spacing of the long nets listed in the high power impact list.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.