Dual port SRAM having reduced cell size and rectangular shape
US9006841B2 · kind B2 · utility
36Cited by
3References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 22, 2012 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Apr 23, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.