Semiconductor chip package having via hole and semiconductor module thereof
US9006872B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2011 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Sep 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.