Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods
US9007817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Oct 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.