Loading trim address and trim data pairs
US9007867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2013 |
| Grant date | Apr 14, 2015 |
| Priority date | — |
| Expiry date | Jun 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of loading trim address and trim data pairs to a trim register array, and apparatus configured to perform such methods. The methods maintain a correspondence between the trim address and the trim data of each trim address and trim data pair in the trim register array. The trim address of a particular trim address and trim data pair corresponds to a storage location of a trim settings array containing trim settings used in performing operations on an array of memory cells. The trim data of the particular trim address and trim data pair corresponds to data to modify a value of the storage location of the trim settings array corresponding to the trim address of the particular trim address and trim data pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.