Solder joint reflow process for reducing packaging failure rate
US9010617B2 · kind B2 · utility
5Cited by
2References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2011 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Mar 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a reflow process, a plurality of solder bumps between a first workpiece and a second workpiece is melted. During a solidification stage of the plurality of solder bumps, the plurality of solder bumps is cooled at a first cooling rate. After the solidification stage is finished, the plurality of solder bumps is cooled at a second cooling rate lower than the first cooling rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.