MOS transistor on SOI protected against overvoltages
US9012955B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 19, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
A MOS transistor protected against overvoltages formed in an SOI-type semiconductor layer arranged on an insulating layer itself arranged on a semiconductor substrate including a lateral field-effect control thyristor formed in the substrate at least partly under the MOS transistor, a field-effect turn-on region of the thyristor extending under at least a portion of a main electrode of the MOS transistor and being separated therefrom by said insulating layer, the anode and the cathode of the thyristor being respectively connected to the drain and to the source of the MOS transistor, whereby the thyristor turns on in case of a positive overvoltage between the drain and the source of the MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.