Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips
US9013022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Aug 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.