Active memory data compression system and method
US9015390B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 2003 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Oct 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit active memory device receives task commands from a component in a host computer system that may include the active memory device. The host system includes a memory controller coupling the active memory device to a host CPU and a mass storage device. The active memory device includes a command engine issuing instructions responsive to the task commands to either an array control unit or a DRAM control unit. The instructions provided to the DRAM control unit cause data to be written to or read from a DRAM and coupled to or from either the processing elements or a host/memory interface. The processing elements execute instructions provided by the array control unit to decompress data written to the DRAM through the host/memory interface and compress data read from the DRAM through the host/memory interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.