Chip select (‘CS’) multiplication in a serial peripheral interface (‘SPI’) system
US9015394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2012 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Oct 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Chip select (‘CS’) multiplication in an SPI system that includes an SPI master, a CS multiplier, a plurality of SPI slaves, and a fall time detection circuit, where the SPI master is coupled to the CS multiplier and the fall time detection circuit by a CS signal line, the CS multiplier includes a plurality of CS outputs with each CS output coupled to an SPI slave, and CS multiplication includes: receiving, from the SPI master, the CS signal on the CS signal line; detecting fall time of the CS signal; and, if the fall time of the CS signal is less than a predefined threshold, configuring, by the fall-time detection circuit, the CS multiplier to vary from providing a CS signal on a first CS output to providing a CS signal on a second CS output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.