Method and apparatus for DMA transfer with synchronization optimization
US9015397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2013 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Oct 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.