Efficient state transition among multiple programs on multi-threaded processors by executing cache priming program
US9015720B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2009 |
| Grant date | Apr 21, 2015 |
| Priority date | — |
| Expiry date | Apr 21, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or the program itself change, is described. An embodiment of the invention supports a “cache priming program” that is selectively executed for a first thread/program/sub-routine of each process. Such a program is optimized for situations when instructions and other program data are not yet resident in cache(s), and/or whenever resources required for program execution or the program itself changes. By pre-loading the cache with two resources required for two instructions for only a first thread, average thread latency is reduced because the resources are already present in the cache. Since, such a mechanism is carried out only for one thread in a program cycle, pitfalls of a conventional general pre-fetch scheme that involves parsing of the program in advance to determine which resources and instructions will be needed at a later time, are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.