Semiconductor device processing with reduced wiring puddle formation

US9018097B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Thomas W. Dyer · Pleasant Valley, US
• Hanako Henry · Newburgh, US
• Tze-man Ko · Hopewell Junction, US
• Yiheng Xu · Hopewell Junction, US
• Shaoning Yao · Wappingers Falls, US

Key dates

• Filing date: Oct 10, 2012
• Grant date: Apr 28, 2015
• Expiry date: Jun 28, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76802
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.