Nonvolatile memory structure and fabrication method thereof
US9018691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Jul 17, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.