Management of cache size
US9021207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2012 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Jul 31, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.