Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes
US9021293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.