Register protected against fault attacks
US9021316B2 · kind B2 · utility
2Cited by
2References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 7, 2013 |
| Grant date | Apr 28, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method of detecting a fault attack in a circuit includes a plurality of registers each identified by an address. The method includes storing in a memory the address present on an address bus during a write operation to one of said registers. In response to a first alert signal indicating that the data stored by a first of said registers has been modified, comparing the address identifying said first register with said stored address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.