Circuit and layout techniques for flop tray area and power otimization
US9024658B2 · kind B2 · utility
2Cited by
11References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2013 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Jun 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.