Jay M. Shah
10Patents
4h-index
32Co-inventors
49Inventor score
Filing activity: Oct 3, 2011 → Aug 18, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9070552B1 | Adaptive standard cell architecture and layout techniques for low area digital SoC | Electricity | 15 | Active |
| US9196707B2 | Oxygen scavenging spacer for a gate electrode | Electricity | 4 | Active |
| US9397101B2 | Stacked common gate finFET devices for area optimization | Electricity | 4 | Active |
| US9059211B2 | Oxygen scavenging spacer for a gate electrode | Electricity | 4 | Active |
| US9093495B2 | Method and structure to reduce FET threshold voltage shift due to oxygen diffusion | Electricity | 3 | Active |
| US9589658B1 | Disturb free bitcell and array | Physics | 3 | Active |
| US9024658B2 | Circuit and layout techniques for flop tray area and power otimization | Physics | 2 | Active |
| US9673786B2 | Flip-flop with reduced retention voltage | Electricity | 0 | Active |
| US8564074B2 | Self-limiting oxygen seal for high-K dielectric and design structure | Electricity | 0 | Active |
| US9431289B2 | Method and structure to reduce FET threshold voltage shift due to oxygen diffusion | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.