Patent · US Active

Clock glitch detection circuit

US9024663B2 · kind B2 · utility

1Cited by

21References

20Claims

0Family size

Assignee

Freeescale Semiconductor, Inc. · US

Inventors

Michael Rohleder · Unterschleißheim, DE
Thomas Koch · Kleinwallstadt, DE
Vladimir Litovtchenko · Ebersberg, DE
Thomas Henry Luedeke · Oberbergkirchen, DE

Key dates

Filing date	Aug 30, 2013
Grant date	May 5, 2015
Priority date	—
Expiry date	Aug 30, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/1252
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.