Tessellation shader inter-thread coordination
US9024946B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2010 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Oct 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention sets forth a technique for performing a computer-implemented method for tessellating patches. An input block is received that defines a plurality of input patch attributes for each patch as well as instructions for processing each input patch. A plurality of threads is launched to execute the instructions to generate each vertex of a corresponding output patch based on the input patch. Reads of values written during instruction execution are synchronized so threads can read and further process the values of other threads. An output patch is then assembled from the outputs of each of the threads; and emitting the output patch for further processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.