Detecting and reissuing of loop instructions in reorder structure
US9026769B1 · kind B1 · utility
40Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jan 24, 2012 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Oct 15, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor for processing loop instructions can include an instruction reorder structure and a loop processing controller. The instruction reorder structure is configured to store decoded instructions according to program order and issue the decoded instructions for execution out of program order. The loop processing controller is configured to detect a loop in the decoded instructions stored in the instruction reorder structure and cause the instruction reorder structure to reissue the decoded instructions that form the loop for re-execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.