Co-simulation methodology to address performance and runtime challenges of gate level simulations with, SDF timing using emulators
US9026966B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | May 5, 2015 |
| Priority date | — |
| Expiry date | Mar 13, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present patent document relates to a method and apparatus for more efficiently simulating a circuit design (DUT), making use of a hardware functional verification device such as a processor-based emulator. A set of linked databases are compiled for the DUT, one for hardware emulation (without timing information for the DUT) and one for software simulation (including timing information) that remain synchronized during runtime. The compiled design is run in a hardware emulator during an initialization/configuration phase and the state saved. The state is then swapped to a software simulator where timing information, such as SDF timing, may be honored during the second part of the run and the user's test bench stimuli applied to the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.