Vertical semiconductor device comprising a resurf structure
US9035415B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2011 |
| Grant date | May 19, 2015 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/157
Abstract
A technology for a vertical semiconductor device having a RESURF structure, which is capable of preventing the drop of the withstand voltage when the adhesion of external electric charges occurs is provided. The vertical semiconductor device disclosed in the present specification has a cell region and a non-cell region disposed outside the cell region. This vertical semiconductor device has a diffusion layer disposed in at least part of the non-cell region. When the vertical semiconductor device is viewed in a plane, the diffusion layer has an impurity surface density higher than that satisfying a RESURF condition at an end part close to the cell region, and an impurity surface density lower than that satisfying the RESURF condition at an end part far from the cell region. When the vertical semiconductor device is viewed in a plane, a region in the diffusion layer that has the impurity surface density higher than that satisfying the RESURF condition has a greater mean gradient of the impurity surface density than a region in the diffusion layer that has the impurity surface density lower than that satisfying the RESURF condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.